1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for distributing signals through jig-plates which hold chips in place in a computer system.
2. Related Art
Many systems require semiconductor chips to be assembled into a computer system with very precise alignment. For instance, systems in which chips communicate via capacitive coupling require chips to be precisely aligned to facilitate the capacitive communication between the chips.
The need for precise alignment is not limited to systems that use capacitive coupling. For example, chips communicating through traditional conductive connections may also require careful alignment. Furthermore, imaging applications where multiple tiled chips comprise a single display may require very accurate chip placement.
Designers can use an alignment plate, or a “jig-plate,” to achieve this precise chip-to-chip alignment. A number of alignment features can be used to achieve this alignment, such as registration posts, grooves, edges or cutouts. In one example, a jig-plate may include cut-out openings which are configured to receive semiconductor chips. These cut-outs are formed with sufficient accuracy to ensure that the chips align properly. In many applications, the alignment tolerances are within fractions of a micron.
For example, FIG. 1 illustrates a jig-plate with nine cutouts. Note that the chips which are inserted into these cutouts are precisely aligned with respect to the other chips in the jig-plate. This type of jig-plate can be used in applications such as an imaging chip array.
FIG. 2 illustrates another type of jig-plate which has four deep cutouts (marked with hashes) and four shallow cutouts (marked in white). In this jig-plate, four chips can be placed face-up in the deep cutouts and another four chips can be placed face-down in the shallow cutouts, thereby facilitating corner-wise capacitively coupled communication between the chips.
In addition to the alignment requirements, systems typically require a small number of signals to be distributed across all chips in the system. For example, a global clock signal is typically distributed from a common source to each component in a synchronous system. In asynchronous systems, a secondary clock signal, which is used solely for testing, telemetry, and debugging, can be distributed from a common source to each component that requires it. In addition, some in-order processor architectures make use of a “stall” signal which is transmitted from a single control source to every computational unit.
Distributing such signals across existing chip-to-chip interfaces creates significant complications. Chips run at different speeds, so signals traversing different chips encounter different delays, which can cause sizable system-wide skew. In addition, different chips are subject to different time-varying power-supply voltages, signal activity levels, temperature, and noise, which can cause considerable jitter in the broadcast signals. Moreover, providing pathways for these signals through chip-to-chip interfaces consumes metallization and transistor resources on the chips themselves.
Hence, what is needed is a method and an apparatus for distributing signals in a system without the above-described performance problems.